1. Field of the Invention
This invention generally relates to a semiconductor device, and more particularly, to a non-volatile semiconductor memory device and a method of fabricating the same.
2. Background of the Invention
Flash memory is a type of non-volatile memory, which can retain its content without consumption of power and can be written to and erased multiple times. One type of flash memory stores information in an array of floating gate transistors, each of which (called “cell”) generally stores one bit of information. Newer devices, sometimes referred to as multi-level-cell devices, may store more than one bit per cell, by using more than two levels of electrical charge placed on the floating gate of a cell. Multi-level-cell devices may double memory capacity but they may suffer slower reading and write operations.
One type of flash memory is known as nitride read only memory. Nitride read only memory may include an array of nitride read only memory cells for data storage. Each nitride read only memory cell may include a source, a drain and a gate structure formed on a p-type substrate. The gate structure may include a polysilicon layer overlaying an oxide/nitride/oxide (ONO) stacked layer, with the nitride layer serving as charge trapping layer. Each nitride read only memory cell may store one or more bits of data. For example, dual bit memory devices allow storage of two bits of data in a single cell, one bit being stored in the trapping layer proximate to the source region and the other being stored in the trapping layer proximate to the drain region.
In multi-bit memory devices that utilize an ONO stacked layer to store charges, the charge added or removed during programming (i.e., write) and erase operations should be confined to the respective source and drain regions of a cell. However, in reality, as gate length is scaled down below 65 nm, the charges in one of the source and drain regions may overlap with the charges in the other region, thus changing the reading, programming and erase characteristics of the cell over time. Eventually, the overlap of two groups of charges changes the threshold voltages for determining the state of the respective bits in a cell and thus causes unreliable bit sensing.
In addition, a memory with a floating gate structure may encounter the issue of stress-induced leakage current, especially when the memory device shrinks (i.e., the memory has a thinner tunnel oxide film) and when the voltage is applied on the drain terminal of a memory cell. In other words, the memory device may have a leakage path at a weak point on the tunnel oxide film and thus the data is lost through the leakage path.